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A hybrid embedded developing and debugging system for satellite navigation terminal design
会议论文
Bremen, Germany, October 1, 2018 - October 5, 2018
作者:
Jiang, Ling
;
Yuan, Huoping
收藏
  |  
浏览/下载:21/0
  |  
提交时间:2019/06/25
A Low-Noise 56Gbps PAM-4 Linear Optical Receiver in 40nm CMOS
会议论文
作者:
Yao, Ting-Yu
;
Li, Dan
;
Xie, Yang
;
Chiang, Patrick Yin
;
Hong, Zhi-Liang
收藏
  |  
浏览/下载:8/0
  |  
提交时间:2019/11/19
A Ka Band Multi-channel Integrated Receiver for Passive Millimeter Wave Imaging System
会议论文
2018 PROGRESS IN ELECTROMAGNETICS RESEARCH SYMPOSIUM (PIERS-TOYAMA), 2018-01-01
作者:
Chen, Xi
;
Ye, Xiuzhu
;
Wang, Chao
;
Hu, Anyong
;
Miao, Jungang
收藏
  |  
浏览/下载:4/0
  |  
提交时间:2019/12/30
AN INTEGRATED GNSS REMOTE SENSING INSTRUMENT AND ITS FIRST GNSS-R AIRBORNE EXPERIMENT
会议论文
36th IEEE International Geoscience and Remote Sensing Symposium (IGARSS), Beijing, PEOPLES R CHINA, JUL 10-15, 2016
作者:
Wang, Xianyi
;
Sun, Yueqiang
;
Du, Qifei
;
Wang, Dongwei
;
Wu, Di
收藏
  |  
浏览/下载:17/0
  |  
提交时间:2017/04/07
GNSS
Remote Sensing
DDM
Airborne Experiment
A 25Gb/s 3D-Integrated Silicon Photonics Receiver in 65nm CMOS and PIC25G for 100GbE Optical Links
会议论文
作者:
Li, Dan
;
Minoia, Gabriele
;
Repossi, Matteo
;
Baldi, Daniele
;
Ghilioni, Andrea
收藏
  |  
浏览/下载:14/0
  |  
提交时间:2019/12/02
silicon photonics
limiting amplifier
output buffer
3D integration
transimpedance amplifier (TIA)
Ge-PD
optical receiver
A CMOS circuit design of a loss of signal and the application in optical receivers
会议论文
2011 International Symposium on Integrated Circuits, SingaporeSingapore, Singapore
作者:
Feiyan Qin
;
Guoqing Xu
;
Huiyun Li
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  |  
浏览/下载:9/0
  |  
提交时间:2015/08/25
A new approach to realize UART (EI CONFERENCE)
会议论文
2011 International Conference on Electronic and Mechanical Engineering and Information Technology, EMEIT 2011, August 12, 2011 - August 14, 2011, Harbin, China
Wang Y.
;
Song K.
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  |  
浏览/下载:23/0
  |  
提交时间:2013/03/25
In order to connect DSP which has synchronous serial ports to the devices implementing asynchronous communications protocol
a method to implement UART communications based on programmable logic device is proposed in the paper. In the proposed method
the core function of UART is integrated in CPLD with VHDL. Firstly
UART data frame format and operational principle of UART were introduced after reviewing some methods to realize UART. The methods to implement UART transmitter
UART receiver and baudrate generator using VHDL were illustrated in detail. Then pre-simulation and synthesize of VHDL program were executed. Finally
the test with bit error rate was carried out on physical system. Experimental results indicate that 75 percent of the GLB are used by UART
and the bit error rate is less than 109. The experiment was implemented utilizing the RS-422 protocol and the baudrate is 62.5kb/s. The proposed method can satisfy the system requirements of high integration
stabilization
low bit error rate
strong anti-jamming and low cost. 2011 IEEE.
Towards Low Frequency Low Noise Low Power Body Sensor Network-on-Chip
会议论文
1st International Conference on Green Circuits and Systems, ICGCS 2010, Shanghai, China
作者:
Jinyong Zhang
;
Zedong Nie
;
Jin Huang
;
Li Yu
;
Lei Wang
收藏
  |  
浏览/下载:13/0
  |  
提交时间:2015/08/21
A 5Gb/s Optical Receiver Front-End in 0.18 mu m CMOS Technology
会议论文
PROCEEDINGS OF 2009 INTERNATIONAL WORKSHOP ON INFORMATION SECURITY AND APPLICATION
作者:
An Qi
;
Li lei
;
Liang yuanjun
;
Ke Lingzhi
收藏
  |  
浏览/下载:6/0
  |  
提交时间:2015/08/21
Double-crystal probe with one transmitter and multiple receivers for automatic inspection
会议论文
Liu, Qingkai
;
Liu, Jiarui
收藏
  |  
浏览/下载:2/0
  |  
提交时间:2015/11/13
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