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	SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures
	Gao, Lan; Wang, Rui; Xu, Yunlong; Yang, Hailong; Luan, Zhongzhi; Qian, Depei; Zhang, Han; Cai, Jihong
刊名	JOURNAL OF SUPERCOMPUTING
	2018
卷号	74页码:3388-3414
关键词	CPU-GPU heterogeneous architectures Hybrid cache Shared memory STT-RAM
ISSN号	0920-8542
DOI	10.1007/s11227-018-2389-3
URL标识	查看原文
收录类别	SCIE
WOS记录号	WOS:000437753700021
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/5932625
专题	北京航空航天大学
推荐引用方式 GB/T 7714	Gao, Lan,Wang, Rui,Xu, Yunlong,et al. SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures[J]. JOURNAL OF SUPERCOMPUTING,2018,74:3388-3414.
APA	Gao, Lan.,Wang, Rui.,Xu, Yunlong.,Yang, Hailong.,Luan, Zhongzhi.,...&Cai, Jihong.(2018).SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures.JOURNAL OF SUPERCOMPUTING,74,3388-3414.
MLA	Gao, Lan,et al."SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures".JOURNAL OF SUPERCOMPUTING 74(2018):3388-3414.

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